Problems and approaches for a Teraflop processor

Authors:
A. H. Frey;G. C. Fox
Affiliations:
IBM and Computer Science Department, California Institute of Technology, Pasadena, CA;Professor of Theoretical Physics, California Institute of Technology, Pasadena, CA
Venue:
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Year:
1988

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Abstract

This paper discusses problems associated with designing a processor capable of sustaining a teraflop (1012 floating point operations per second) of processing power. Several researcher have speculated on achieving this performance. The technical problems of a practical design are shown to be formidable. However, none of these problems requires a technology breakthrough for their solution. The predictable advances of the next generation of technology together with a major engineering effort is all that will be required to build such a parallel machine with usable teraflop processing power.