A programming model for the Mark III hypercube with multiple processor nodes

Authors:
B. A. Zimmermann;G. A. Crichton
Affiliations:
Jet Propulsion Laboratory, California Institute of Technology;Jet Propulsion Laboratory, California Institute of Technology
Venue:
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
Year:
1988

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Solving problems on concurrent processors. Vol. 1: General techniques and regular problems
Solution of a problem in concurrent programming control

Communications of the ACM

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Abstract

The Caltech/JPL Mark III Hypercube originally consisted of an ensemble of processing elements each containing two Motorola M68020 processors — one M68020 processor and a M68881 Floating-Point coprocessor used for data processing, the other M68020 processor dedicated to hypercube communications. In the interest of achieving even greater computational capability a third processing element, the Weitek XL system, was added to enhance floating point performance. Each of what is now three processing elements is configured with CPU, local static memory, communication peripherals, clocks, and control logic. In addition, they share 4 megabytes of dynamic memory on the node card. We will describe a programming model and environment that accommodates the operation of the three processors, preparation, extended Crystalline communications, and intranode concurrency.