HPSm, a high performance restricted data flow architecture having minimal functionality
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
HPS, a new microarchitecture: rationale and introduction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
The hardware architecture of the CRISP microprocessor
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
The performance potential of multiple functional unit processors
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Hierarchical registers for scientific computers
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Decoupled access/execute computer architectures
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Efficient Instruction Sequencing with Inline Target Insertion
IEEE Transactions on Computers
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In this paper we evaluate the performance of single-chip processors with multiple functional units. As a basis for our studies we use a processor model that is very similar to many of today's single-chip processors. Using this basic machine model, we investigate the performance that can be achieved if some limited form of multiple instruction issue is supported. For these investigations, we use 4 variants of the basic machine that represented different memory access times and branch execution times. In particular, we evaluate issuing 2 instructions per cycle and find that by restricting multiple instruction issue to load or branch instructions much of the same performance gains can be achieved as in the unrestricted form.