A high-speed hardware unit for a subset of logic resolution

  • Authors:

  • D. Wong

  • Affiliations:

  • Department of Electrical Engineering, Stanford University, Stanford, California

  • Venue:
  • MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
  • Year:
  • 1988

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Abstract

High-speed engines for logic programming have been the target of much recent research. Here, we present a high-level hardware design and its custom data formats for directly performing a subset of logic resolution. This design uses parallelism in unifying arguments and substituting variable bindings which is distinct from the widely discussed OR and AND parallelism.