Cache design of a sub-micron CMOS system/370
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
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The implementation of the &mgr;-sequencer and the large loadable control store of a high performance CMOS 370 system [1] is described. The control store consists of two parts, a small on-chip control store and a main control store. A small on-chip control store keeps the first two control words of each &mgr;-sequence. A large main control store contains the remaining control words of each &mgr;-sequence. The small control store is implemented so that there is no need to include an extra pipeline stage to start an instruction execution in order to achieve a short cycle time. With a short cycle time, the access of the large control store takes at least two cycles to complete. In order to get one control word every cycle, the access to the control store is pipelined. A static &mgr;-branch prediction scheme is used to generate the next &mgr;-address ahead of the determination of a &mgr;-branch. With this scheme, an effectively one-cycle access from a large loadable control store can be achieved without affecting the machine cycle time.