Parallel Decoding Cyclic Burst Error Correcting Codes
IEEE Transactions on Computers
| Hi-index | 0.00 |
This paper presents a scheme of ultra-fast one-shot Reed-Solomon decoding (prototyped (40-34,32,8) soft-IP demonstrating over 7Gb/s using 0.35 um ASIC technology) and discusses its application to future dependable computer systems, taking a redundant array memory system as an example. We compare different memory configurations and identify improved fault-tolerance to single-bit failures as well as chip and card failures for smaller system overheads when random quad-byte one-shot Reed-Solomon decoding is used. We also discuss an alternative use of the powerful coding gain, i.e., an application to the dynamic refresh interval control of DRAMs, in order to optimize the refresh overheads in performance and power consumption. We believe that the one-shot Reed-Solomon decoding offers an advanced error correction capability for various parts of future high-performance computer systems, where system-level reliability can suffer because of rapidly increasing data size and speed.