An On-Line Reconfigurable FPGA Architecture

• Authors: Parag K. Lala;Alvernon Walker
• Venue: DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
• Year: 2000

FPGAs are widely used for prototyping of digital systems. A major problem of current FPGA architectures is that if a there is a fault in a single combinational logic block (CLB), it may take a significant amount of time to find an alternative mapping of the circuit to bypass the faulty block. Thus, there is a need for new type FPGA architectures that allow rapid recovery from internal faults in a FPGA. Currently only the detection of permanent faults in logic blocks, and on their interconnections are considered in FPGA-based systems. Several studies in recent years have shown that transient faults are likely to occur at a much higher rate than permanent faults in submicron VLSI devices. The only way to cope with transient faults in FPGAs is to detect them as soon as they occur, and perform on-line reconfiguration to recover from their effects. This paper presents a reconfigurable FPGA architecture that enables on-line fault detection in the constituent CLBs of the FPGA.