A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques

Authors:
S. Blanc;J. Gracia;P. J. Gil
Affiliations:
-;-;-
Venue:
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
2002

Citing 0
Cited 3

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Abstract

Fault injection techniques are frequently used for validating dependable systems. VHDL-based techniques are good resources that support fault injection with many advantages such as a high level of accessibility, controllability and precision. This paper presents the results obtained with a VHDL-based tool (VFIT) injecting single and multiple faults at pin-level in a TTP/C model. The study is focused on the fault hypothesis of a modelled communications protocol based on the Time-Triggered Architecture. Results are analysed and compared with the experiments carried out in the real prototyped system with a pin-level fault injection tool (AFIT). Conclusions strengthen the usability of VHDL-based fault injection tools and reveal technique weaknesses.