Data structures and network algorithms
Data structures and network algorithms
Fibonacci heaps and their uses in improved network optimization algorithms
Journal of the ACM (JACM)
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
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State-of-the-art FPGAs possess I/O resources that can be configured to support a wide variety of I/O standards [1]. In such devices, the I/O resources are grouped into banks. One of the consequences of the banked organization is that all of the I/O objects that are placed within a bank must use "compatible" I/O standards. The compatibility of I/O standards is based on each standard's supply and reference voltage requirements. For designs that use more than one I/O standard, the constraints associated with the banked organization lead to a constrained I/O pad placement problem. Meeting these constraints with a minimal deleterious effect on traditional objectives like minimizing wirelength turns out to be quite challenging. In this paper, we present a placement algorithm that operates in the context of these constraints. Our approach uses a combination of simulated annealing, weighted bipartite matching and constructive packing to produce a feasible I/O placement. Results show that the proposed algorithm produces placements with wirelength characteristics that are similar to the placements produced when pad placement is unconstrained.