FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers

Authors:
Bogdan Matasaru;Tudor Jebelean
Affiliations:
-;-
Venue:
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Year:
2000

Citing 4
Cited 0

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The accelerated integer GCD algorithm

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Bidirectional exact integer division

Journal of Symbolic Computation - Special issue on parallel symbolic computation
A Subroutine for Computations with Rational Numbers

Journal of the ACM (JACM)

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Abstract

We present the FPGA implementation of an extension of the binary plus-minus systolic algorithm which computes the GCD (greatest common divisor) and also the normal form of a rational number, without using division. A sample array for 8 bit operands consumes 83.4% of an Atmel 40K10 chip and operates at 25 MHz.