Data Dependent Circuit for Subgraph Isomorphism Problem

Authors:
Shuichi Ichikawa;Shoji Yamamoto
Affiliations:
-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

Citing 2
Cited 1

An Algorithm for Subgraph Isomorphism

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Evaluation of Accelerator Designs for Subgraph Isomorphism Problem

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Fast digital signature algorithm based on subgraph isomorphism

CANS'07 Proceedings of the 6th international conference on Cryptology and network security

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Abstract

The subgraph isomorphism problem has various important applications, although it is generally NP-complete and difficult to solve. This paper examines the feasibility of a data dependent circuit for the subgraph isomorphism problem, which is particularly suitable for FPGA implementation. For graphs of 32 vertices, the average logic scale of data dependent circuits is only 5% of the corresponding data independent circuit. The circuit is estimated to be 460 times faster than the software for 32 vertices. Even if the circuit generation time is included, a data dependent circuit is expected to be two times faster than software when there are 32 vertices. For larger graphs, the performance gain would be far larger.