A hierarchical associative processing system
A hierarchical associative processing system
LUCAS associative array processor: design, programming and application studies
LUCAS associative array processor: design, programming and application studies
The Maximum and Minimum Selector SELRAM and its Application for Developing Fast Sorting Machines
IEEE Transactions on Computers
Supercomputing for solving a class of NP-complete and isomorphic complete problems
Computer Systems Science and Engineering
Sequential and parallel processing in depth search machines
Sequential and parallel processing in depth search machines
Associative Processor Architecture—a Survey
ACM Computing Surveys (CSUR)
Content Addressable Parallel Processors
Content Addressable Parallel Processors
Associative Processing and Processors
Associative Processing and Processors
A Search Memory for Many-to-Many Comparisons
IEEE Transactions on Computers
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The multi-comparand associative search paradigm is shown to be efficient in processing complex search problems from many application areas including computational geometry, graph theory, and list/matrix computations. In this paper the first FPGA implementation of a small multi-comparand multi-search associative processor is reported. The architecture of the processor and its functions are described in detail. The processor works in a combined bit-serial/bit-parallel mode. Its main component is a multi-comparand associative memory with up to 16 programmable prescription functions (logic searches). Parameters of implemented FPGA devices are presented and discussed.