An FPGA Co-processor for Real-Time Visual Tracking

Authors:
Miguel Arias-Estrada;Eduardo Rodríguez-Palacios
Affiliations:
-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

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Abstract

This paper presents the design overview and the post-synthesis simulation results of a digital co-processor for real-time visual tracking implemented in a Virtex-E field programmable gate array. The hardware description of the system was made in VHDL and the simulations show that the system performs up to 79 frames per second in a half-resolution VGA image format (320 脳 240 pixels). The co-processor calculates edge/corner detection, stationary background and noise filtering, and the distance transform algorithm; these optimized operations implemented in the FPGA and the Hausdorff distance algorithm programmed in a general purpose processor implement a real-time visual tracking system.