Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping

  • Authors:

  • Thomas Buerner

  • Affiliations:

  • -

  • Venue:
  • FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
  • Year:
  • 2002

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Abstract

A major problem in simulating communication systems is that, below a certain error rate, software simulation is too slow. Also software often does not allow to simulate the real system but only a somehow simplified version. Rapid prototyping can help to execute a hardware emulation of the system that is fast and represents the real behaviour too. As an example this paper describes the software simulation and hardware emulation of an extended BCH(16,7) code over an additive white Gaussian noise(AWGN) channel using binary phase shift keying (BPSK). Successive erasure decoding(SED) shows an additional gain of about 1 dB at a bit error rate of 10-6 and below, compared to a standard Berlekamp-Massey algorithm(BMA).The first two sections present the theoretical coding background, section three deals with implementation issues and section four discusses simulation and emulation results.1