Using Design Hierarchy to Improve Quality of Results in FPGAs

Authors:
Alireza Kaviani
Affiliations:
-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

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Abstract

This paper presents and analyzes a methodology for improving the quality of results in Field Programmable Gate Arrays (FPGAs) by taking advantage of the design hierarchy. We use a representative case study, which is a real design, to demonstrate how taking advantage of the hierarchy may lead to higher area-efficiency and better speed-performance. According to our results, an area saving of 18% along with a speedup of 15% is achievable; these area and speed improvements may result in a cost saving of a factor of two for volume production. Our analysis also shows that the above savings will not have a negative impact on routability and power consumption.