Algorithms from P to NP (vol. 1): design and efficiency
Algorithms from P to NP (vol. 1): design and efficiency
Achieving Board-Level BIST Using the Boundary-Scan Master
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects
EDTC '96 Proceedings of the 1996 European conference on Design and Test
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Testing for Faults in Wiring Networks
IEEE Transactions on Computers
Testing and diagnosis of interconnects using boundary scan architecture
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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The interconnect BIST is achieved by the on-linepolling for the composite vectors that contain the encoded information for the test generation and responseevaluation on selective drivers and receivers to adaptto the changing configuration.