Theoretical Computer Science
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
An introduction to ET-LOTOS for the description of time-sensitive systems
Computer Networks and ISDN Systems
Communication and Concurrency
Multimedia in Temporal LOTOS: A Lip-Synchronization Algorithm
Proceedings of the IFIP TC6/WG6.1 Thirteenth International Symposium on Protocol Specification, Testing and Verification XIII
Compositional Specification of Timed Systems (Extended Abstract)
STACS '96 Proceedings of the 13th Annual Symposium on Theoretical Aspects of Computer Science
Modeling Urgency in Timed Systems
COMPOS'97 Revised Lectures from the International Symposium on Compositionality: The Significant Difference
HYTECH: The Cornell HYbrid TECHnology Tool
Hybrid Systems II
On the Composition of Hybrid Systems
HSCC '98 Proceedings of the First International Workshop on Hybrid Systems: Computation and Control
An Overview and Synthesis on Timed Process Algebras
Proceedings of the Real-Time: Theory in Practice, REX Workshop
The coarsest congruence for timed automata with deadlines contained in bisimulation
CONCUR 2005 - Concurrency Theory
Specifying Urgency in Timed I/O Automata
SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
Compositional Abstraction in Real-Time Model Checking
FORMATS '08 Proceedings of the 6th international conference on Formal Modeling and Analysis of Timed Systems
A Tool for the Syntactic Detection of Zeno-timelocks in Timed Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Reconciling urgency and variable abstraction in a hybrid compositional setting
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Performance verification in complex enterprise-level component systems
FACS'10 Proceedings of the 7th international conference on Formal Aspects of Component Software
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We address the issue of modelling a simple timeout in timed automata. We argue that expression of the timeout in the UPPAAL timed automata model is unsatisfactory. Specifically, the solutions we explore either allow timelocks or are prohibitively complex. In response we consider timed automata with deadlines which have the property that timelocks cannot be created when composing automata in parallel. We explore a number of different options for reformulating the timeout in this framework and then we relate them.