Design and validation of computer protocols
Design and validation of computer protocols
Theoretical Computer Science
Systems Engineering Using SDL-92
Systems Engineering Using SDL-92
Validating SDL Specifications: an Experiment
Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX
Embedding a Dialect of SDL in PROMELA
Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking
Integrating Real Time into Spin: A Prototype Implementation
FORTE XI / PSTV XVIII '98 Proceedings of the FIP TC6 WG6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols (FORTE XI) and Protocol Specification, Testing and Verification (PSTV XVIII)
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A Formal Object-Oriented Analysis for Software Reliability: Design for Verification
FASE '01 Proceedings of the 4th International Conference on Fundamental Approaches to Software Engineering
Extending the Translation from SDL to Promela
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
SDLcheck: A Model Checking Tool
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Basic-REAL: Integrated Approach for Design, Specification and Verification of Distributed Systems
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
The High Road to Formal Validation
ABZ '08 Proceedings of the 1st international conference on Abstract State Machines, B and Z
| Hi-index | 0.00 |
We present an attempt to use the model checker Spin as a verification engine for SDL, with special emphasis put on the verification of timing properties of SDL models. We have extended Spin with a front-end that allows to translate SDL to Promela (the input language of Spin), and a back-end that allows to analyse timing properties. Compared with the previous attempts, our approach allows to verify not only qualitative but also quantitative aspects of SDL timers, and our translation of SDL to Promela handles the SDL timers in a correct way. We applied the toolset to the verification of a substantial part of a complex industrial protocol. This allowed to expose several non-trivial errors in the protocol's design.