Implementing Associative Search and Responder Resolution

Authors:
Meiduo Wu;Robert A. Walker;Jerry L. Potter
Affiliations:
-;-;-
Venue:
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Year:
2002

Citing 4
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Abstract

In a paper presented last year at WMPP'01 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). That paper presented an overview of the design, and concentrated on the processor's instruction set and its implementation using FPLDs. This paper describes the implementation of the processor's associative operation -- associative searching and responder resolution -- in more detail.