Performance comparison of ILP machines with cycle time evaluation
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Proceedings of the 24th annual international symposium on Computer architecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
The MIPS R10000 Superscalar Microprocessor
IEEE Micro
A Variable Latency Pipelined Floating-Point Adder
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
The Alpha 21264 Microprocessor Architecture
ICCD '98 Proceedings of the International Conference on Computer Design
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Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed.T he delay of the logic imposes the execution time budget to be reduced significantly, resulting in that the execution stage is divided into several stages.V ariable latency pipeline (VLP) structure has the advantages of pipelining and pseudo-asynchronous design techniques.Ac cording to source operands delivered to arithmetic units, the VLP changes execution latency and thus it achieves both high speed and low latency for most of the operands. In this paper we evaluate the VLP on dynamically scheduled superscalar processors using a cycle-by-cycle simulator. Our experimental results show that the VLP is effective for reducing the effective execution time, and thus the constraints on the operand bypass logic is mitigated.W e also evaluate instruction reuse technique in order to support the VLP.