Cooperative shared memory: software and hardware for scalable multiprocessor
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons
ACM Computing Surveys (CSUR)
Journal of Parallel and Distributed Computing
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Selective, accurate, and timely self-invalidation using last-touch prediction
Proceedings of the 27th annual international symposium on Computer architecture
International Journal of Parallel Programming
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The technology and application trends leading to current day multiprocessor architectures such as chip multiprocessors, embedded architectures, and massively parallel architectures, demand faster, more efficient, and more scalable cache coherence schemes than the existing ones. In this paper we present a new scheme that has a potential to meet such a demand. The software support for our scheme is in the form of program annotations to detect shared accesses as well as release synchronizations that represent data sharing boundaries. A small hard-ware called Coherence Buffer (CB) with an associated controller, local to each processor forms the control unit to locally enforce cache coherence actions which are off the critical path. Our simulation study shows that a 8 entry 4-way associative CB helps achieve a speedup of 1.07 - 4.31 over full-map 3-hop directory scheme for five of the SPLASH-2 benchmarks (representative of migratory sharing, producer-consumer and write-many workloads), under Release Consistency model.