A novel ultra-fast heuristic for VLSI CAD steiner trees

Authors:
Bharat Krishna;C.Y. Roger Chen;Naresh K. Sehgal
Affiliations:
Intel Corporation, Santa Clara, CA;Syracuse University, Syracuse, NY;Intel Corporation, Santa Clara, CA
Venue:
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Year:
2003

Citing 5
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Abstract

In all stages of VLSI chip design, routing estimation is required to account for the effect of interconnects. We propose a fast Steiner tree construction algorithm, which is 3-180 times faster for 10-300 point Steiner trees, and within 2.5% of the length of the Batched-1-Steiner tree. The proposed method can be used as a fast net length estimation tool in VLSI CAD applications, e.g. in the inner cycle of a floorplanning/placement engine.