on Parallel MIMD computation: HEP supercomputer and its applications
on Parallel MIMD computation: HEP supercomputer and its applications
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Stride directed prefetching in scalar processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Compiler support for software-based cache partitioning
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Impulse: Building a Smarter Memory Controller
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Compiler-Controlled Cache Mapping Rules
Compiler-Controlled Cache Mapping Rules
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One of the challenges in designing systems is adopting a design method with compositional properties. Compositional functionality guarantees that two components that each perform a task can be integrated without affecting the semantics of either task. Compositional performance means that two components can be integrated so that the timing of neither components changes, In this paper we describe the hardware and software needed in order to build cache memories that have those compositional properties. This partitioned cache allows the system designer to design individual components of an application program in the knowledge that cache performance is fully deterministic; ie. integrating these components will not affect the performance of any component.