Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Reconfigurable DSP's for Efficient MPEG-4 Video and Audio Decoding
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
An Applications-Based Approach to Measuring DSP Efficiency
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
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The ISO MPEG-4 standard is emerging as the dominant digital video standard, and efficient, programmable MPEG-4 video codecs are paramount for emerging mobile devices that aggregate telecommunications with features including digital video. Efficient QCIF simple profile MPEG-4 video codec algorithms are developed for typical 16-bit, dual execution unit DSPs and the additional impact of tightly coupled, co-processors used to dynamically reconfigure the DSP data path is quantified. Efficient, programmable solutions consuming approximately 63 Mcycles, significantly lower than estimates as high as 400 Mcycles, are generated, while dynamic reconfiguration reduces this cost an additional 20%.