Computer
Multiprocessor Architecture Using an Audit Trail for Fault Tolerance
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
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This paper is presented as an attempt to cover the basic practices and methodologies involved in the area of contemporary fault tolerant computing in a computer design course. Most computer design courses cover design of various components of a computer system and integration of these components to build a system. Unfortunately, fault tolerance is not typically covered in a computer design course.We have identified four steps for our method. First, we are identifying the relative effectiveness of the different approaches in fault tolerant. Second, we are discussing various architectures used in the implementation of fault tolerance. Third, we are providing the performance overview of various architectures used. Fourth, we are covering the trade offs involved with the selection of fault tolerance versus system performance.