Communication and concurrency
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
The benefits of relaxing punctuality
Journal of the ACM (JACM)
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Temporal Logic + Timed Automata: Expressiveness and Decidability
CONCUR '95 Proceedings of the 6th International Conference on Concurrency Theory
Model-Checking for Extended Timed Temporal Logics
FTRTFT '96 Proceedings of the 4th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
Concurrency and Automata on Infinite Sequences
Proceedings of the 5th GI-Conference on Theoretical Computer Science
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
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In this paper we integrate two different approaches for the specification and verification of timed systems being used in control theory and computer science. These are the timed condition/event systems and the timed automata formalisms. Our main result states that timed condition/event systems can be efficiently transformed into timed automata which then can be analyzed automatically.