Integrated design method for flip chip CSP with electrical, thermal and thermo-mechanical qualifications

  • Authors:

  • De-Shin Liu;Chin-Yu Ni;Ching-Yang Chen

  • Affiliations:

  • Department of Mechanical Engineering, National Chung Cheng University, 160, San-Hsing, Ming-Hsiung, Chia-Yi 621, Taiwan, Republic of China;Department of Mechanical Engineering, National Chung Cheng University, 160, San-Hsing, Ming-Hsiung, Chia-Yi 621, Taiwan, Republic of China;Department of Mechanical Engineering, National Chung Cheng University, 160, San-Hsing, Ming-Hsiung, Chia-Yi 621, Taiwan, Republic of China

  • Venue:
  • Finite Elements in Analysis and Design
  • Year:
  • 2003

Quantified Score

Hi-index 0.00

Visualization

Abstract

A new design method involving electrical, thermal and thermo-mechanical characterizations was developed to optimize the geometric parameters and material properties of a flip chip CSP. A two-dimensional nonlinear finite element model was created using the APDL commercial software ANSYS programming technique to connect with the search routines of genetic algorithms. The electrical characterization optimization objective function was used to set the characteristic impedance of the solder bump and corresponded with the first incident voltage adapting the CMOS switch event to reduce the response time delay in the binary command as well as maintaining the chip level efficiency. The thermal resistance determines the package thermal performance; that is, the objective function is to minimize the thermal resistance under certain power dissipation parameters. Thermally induced stress and warpage dominate the thermo-mechanical behavior. The objective function is the minimization of the thermal stress gradients around the chip, bump, underfill and molding compound as well as mechanical warpage in the entire package. The optimization results show that a remarkable strategy for packaging design was achieved.