Hierarchical finite-state machines and their use for digital control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A quick safari through the reconfiguration jungle
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis for Control Automata
Logic Synthesis for Control Automata
An Evolutionary Algorithm for the Synthesis of RAM-Based FSMs
IEA/AIE '02 Proceedings of the 15th international conference on Industrial and engineering applications of artificial intelligence and expert systems: developments in applied artificial intelligence
Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
(Self-)reconfigurable Finite State Machines: Theory and Implementation
Proceedings of the conference on Design, automation and test in Europe
Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
A Configurable Hardware/Software Approach to SAT Solving
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An extension of self-reconfigurable FSM with reduced reconfiguration sequences concept
IMCAS'06 Proceedings of the 5th WSEAS international conference on Instrumentation, measurement, circuits and systems
Hardware implementations of software programs based on hierarchical finite state machine models
Computers and Electrical Engineering
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This paper examines some models of finite state machines (FSMs) that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a way that allows their behavior to be modified before and during run-time. This is achieved either by swapping pre-allocated areas on a chip in partially dynamically reconfigurable FPGAs, or by reloading memory-based cells in statically configured FPGAs. The initial behavioral description is presented in the form of hierarchical graph-schemes that can be formally translated to traditional FSM specifications such as state diagrams and state transition tables. The description supports modularity and a hierarchical structure, both of which are important for modifiable circuits. The results of experiments with software models that permit reconfigurable systems to be simulated and verified and with a hardware implementation of a FSM have shown that such reusable circuits require very limited FPGA resources and they can be reprogrammed in much the same way as for software development.