Efficient Subgraph Isomorphism Detection: A Decomposition Approach
IEEE Transactions on Knowledge and Data Engineering
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction and device count reduction. This paper reports a new technology-independent layout extractor, ESDExtractor, which is capable of extracting all types of ESD devices and answers the demands for ESD design verification. General methodology to extract both intentional and parasitic ESD devices, specific algorithms and implementation methods for efficiencyenhancement are presented, followed by a design example.