An experiment with hardware implementation of edge enhancement filter

  • Authors:
  • Terry W. Griffin;Nelson L. Passos

  • Affiliations:
  • Computer Science Program, Midwestern State University, Wichita Falls, TX;Computer Science Program, Midwestern State University, Wichita Falls, TX

  • Venue:
  • Journal of Computing Sciences in Colleges
  • Year:
  • 2002

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Abstract

The significance of experimenting with hardware and software applications in an undergraduate program must be emphasized given the job market need for system designers with a broad knowledge on the computer science field. Interesting applications can always be found in the field of computer vision. In such a field, a digital image is usually segmented into regions. This paper presents an algorithm used to perform the operation of segmenting an image into regions, more specifically edges, and an experiment with its hardware implementation. The selected algorithm is known as the Laplace algorithm. The experiment is conducted by implementing the algorithm in hardware, or more specifically a Field Programmable Gate Array (FPGA), and then evaluating the required clock cycle required for execution of the algorithm.