Boosting beyond static scheduling in a superscalar processor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Performance and the i860 Microprocessor
IEEE Micro
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The design and development of the million-transistor N10 chip, which is aimed at workstations and supercomputers, is described. This superfast microprocessor is also the company's first chip to use a reduced instruction set. The chip is designed for testability, executes each instruction in one clock cycle, and features on-chip parallelism