An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Bibliography on cyclostationarity
Signal Processing
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This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling DS modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the DS modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the DS modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order DS modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1pF capacitors is designed in a 0.25mm standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.