Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

  • Authors:

  • John G. Maneatis;Jaeha Kim;Iain McClatchie;Jay Maxey;Manjusha Shankaradas

  • Affiliations:

  • True Circuits, Inc., Los Altos, CA;True Circuits, Inc., Los Altos, CA;True Circuits, Inc., Los Altos, CA;Texas Instruments Incorporated, Dallas, TX;Texas Instruments Incorporated, Dallas, TX

  • Venue:
  • Proceedings of the 40th annual Design Automation Conference
  • Year:
  • 2003

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Abstract

A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13μm CMOS, the area is 0.182mm2 and the supply is 1.5V.