Hardware acceleration of JPEG2000 image compression for low-power embedded applications

  • Authors:

  • Darren Freeman;Greg Knowles

  • Affiliations:

  • School of Informatics and Engineering, Flinders University of South Australia, PO BOX 2100, Adelaide, South Australia;School of Informatics and Engineering, Flinders University of South Australia, PO BOX 2100, Adelaide, South Australia

  • Venue:
  • ACSC '03 Proceedings of the 26th Australasian computer science conference - Volume 16
  • Year:
  • 2003

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Abstract

JPEG2000 is ideal as the next-generation still image compression standard, and it is expected to replace JPEG for embedded applications such as digital cameras. These typically require low-power operation, so by combining a low-power microprocessor with a hardware accelerator to form a System on Chip (SoC), the burden of rapidly coding JPEG2000 images is moved to the accelerator. The performance requirements of the processor are significantly relaxed, leading to lower power consumption and potentially cheaper fabrication.An introduction to the benefits and inner workings of JPEG2000 is given. In particular, the ideas behind wavelet compression, arithmetic coding and subband sample coding are discussed. In the case of JPEG2000, the MQ Coder functions as the arithmetic coder while subband samples are coded using the Embedded Block Coding with Optimal Truncation (EBCOT) algorithm.Both the MQ Coder and EBCOT are implemented in the hardware accelerator, with a complete System on Programmable Chip (SoPC) prototype demonstrated here. The prototype runs on an Altera ARM-Based Excalibur chip, type EPXA10F1020C1, tested using the Embedded Linux operating system and custom software. Performance estimates are derived from simulation and synthesis results and they are scalable with the number of block coders used. For the EPXA10 chip we obtain 5 megasamples per second, per coder, with a maximum of 20 coders.Future work includes adding functionality such as a Discrete Wavelet Transform (DWT) engine, optimising for low power, and fabrication of an Application-Specific Integrated Circuit (ASIC) which we expect would give between two to five times the performance provided here, depending upon the silicon process used.