SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An experimental study of four typical test suite reduction techniques
Information and Software Technology
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In this paper an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. We examine some not so popular approaches as a single cone processing, single path oriented propagation and backward justification. We give a new definition for SAT-based test generation and present duality of learning phenomenon. The resultant ATPG system, called SPIRIT, combines the flexibility of SAT-based TPG algorithms with the efficiency of structural TPG algorithms. Experimental results demonstrate the efficiency and robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to generate complete test sets for the ISCAS'85 benchmark circuits and full scan version of the ISCAS'89 benchmark circuits within 3 minutes on a 450 MHz Pentium-III PC.