Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
Syntax-directed translation of concurrent programs into self-timed circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
Testing delay-insensitive circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Path breaker: a tool for the optimal design of speed independent asynchronous controllers
EURO-DAC '92 Proceedings of the conference on European design automation
Testing two-phase transition signaling based self-timed circuits in a synthesis environment
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
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Although the advantages of delay-insensitive and self-timed circuits with respect to speed and operation are known, their advantages in terms of testing are not examined. We focus our attention on testing four-phase handshake signalling based circuits designed using Martin's method. Due to the distributed nature of the control part of a delay-insensitive circuit, it is possible to simultaneously test many non-interfering portions of the circuit, thereby substantially reducing the testing time. In order to ensure that the circuit performs in a delay-insensitive manner even during testing, certain OR gates in the synthesized circuit required to be replaced by OR/C blocks. An OR/C block operates as an OR gate during normal operation and as a C-element during testing. Identification of the OR gates to be replaced by OR/C blocks and the generation of test sequences is performed by analyzing the program flow graph of the given circuit.