MuSiC: an event-flow computer for fast simulation of digital systems
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Concurrent and Comparative Discrete Event Simulation
Concurrent and Comparative Discrete Event Simulation
Unified Methods for VLSI Simulation and Test Generation
Unified Methods for VLSI Simulation and Test Generation
Update-Dataflow Computing: A Way to Supercomputing in Discrete Simulation of Digital Systems
Proceedings of the IFIP 12th World Computer Congress on Algorithms, Software, Architecture - Information Processing '92, Volume 1 - Volume I
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MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting parallelism inherent in a design is most efficient. In comparison to two different dataflow computation schemes and their hardware-accelerated implementations, this paper shows that the strategy of compiler-driven simulation can be combined with the concept of event-(activity)-directed simulation (selective trace simulation) not only for logic simulation but also for concurrent fault simulation. Experiments indicate that there is a performance advantage of eventflow computing over the algorithmically simpler dataflow computing schemes but the advantage is limited, since dataflow computing performance of a MuSiC version with 256 Processing Units already is in the range of 10/sup 7/ to 10/sup 8/ test-vectors times gates evaluated per second.