Journal of Electronic Testing: Theory and Applications
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A new design-for-test technique for reducing SOC test time
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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A method to solve the resource allocation and testscheduling problems together in order to achieveconcurrent test for core-based System-On-Chip (SOC)designs is presented in this paper. The primary objectivefor concurrent SOC test is to reduce test applicationtime. The methodology used in this paper is not limited toany specific Test Access Mechanism (TAM).Additionally, it can also be applied for test budgetingduring the design phase to obtain a tradeoff between testapplication time and SOC pins needed. In this paper, theabove problem is formulated as a well-known 2-dimensionalbin-packing problem. A best-fit heuristicalgorithm is employed to obtain satisfactory results asdemonstrated in Section 3.