Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
We describe a built-in test pattern generation method for delayfaults in scan circuits based on partitioning and storage of testsets. Under this method, a precomputed test set is partitionedinto several sets containing values of primary inputs or statevariables. The on-chip test set is obtained by implementing theCartesian product of the stored sets. The sizes of the sets areminimized before they are stored on-chip in order to reduce thestorage requirements and the test application time. The delayfault model we consider is the transition fault model.