ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
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This paper presents a fault simulation environment thattakes advantage of available models at the behavioraland gate levels of abstraction. The simulation takesplace in VHDL and for fault simulation, special VHDLmodels are written that are capable of propagatingcircuit faults. Behavioral VHDL models propagatefault effects that appear on their input ports; inaddition to this, gate level VHDL models are capableof injecting faults on their output lines. The faultsimulation environment assumes existence of the gatelevel and behavioral models for every component, anduses the appropriate model depending on whether afault belongs to it or another component. A wrappersimulation model that encloses both models of acomponent switches automatically between the models.The wrapper takes care of feedbacks in the sequentialcircuits by always selecting the gate level of acomponent for propagating its own faults. Thisenvironment fits well with the hardware descriptionlanguage settings in which pre-synthesis behavioralmodels, post-synthesis gate-level models and a mixedsimulation environment are available. The papershows a mathematical analysis illustratingperformance improvement of this method over thetraditional gate-level fault simulation.