A server-side pre-linking mechanism for updating embedded clients dynamically
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Reducing memory reference energy with opportunistic virtual caching
Proceedings of the 39th Annual International Symposium on Computer Architecture
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The StrongARM SA-1100 is a high-speed low-power processor aimed at embedded and portable applications. Its architecture features virtual caches and TLBs which are not tagged by an address-space identifier. Consequently, context switches on that processor are potentially very expensive, as they may require complete flushes of TLBs and caches.This paper presents the design of an address-space management technique for the StrongARM which minimizes TLB and cache flushes and thus context switching costs. The basic idea is to implement the top-level of the (hardware-walked) page-table as a cache for page directory entries for different address spaces. This allows switching address spaces with minimal overhead as long as the working sets do not overlap. For small (_ 32 MB) address spaces further improvements are possible by making use of the Strong-ARM's re-mapping facility. Our technique is discussed in the context of the L4 microkernel in which it will be implemented.