Implementation of a SliM Array Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A massively parallel implementation of the watershed based on cellular automata
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
A Linear Array Parallel Image Processor: SliM-II
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
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This paper presents the design and implementation of a Sliding Memory Plane (SliM) Image Processor chip to build a mesh-connected SIMD architecture called a SliM Array Processor. The SliM Image Processor chip consists of 5 x 5 processing elements (PEs) connected by a mesh topology. A set of SliM Image Processor chips can form the SliM Array Processor. Due to the idea of sliding, that is, overlapping inter-PE communication with computation, the SliM Image Processor can greatly reduce the inter-PE communication overhead, a significant disadvantage of existing SIMD array processors. In addition, using the by-passing path provides eight-way connectivity even with four physical links. This paper addresses architectures of the SliM Image Processor chip, the design of an instruction set, and implementation issues. The chip has 55,255 gates and twenty-five 128 x 9-bit SRAM modules, and was simulated at 18 MHz for the worst case conditions, and will actually run at a higher clock rate. The package type is the 144 pin MQFP. We conduct the performance evaluation of the chip that shows a significant improvement.