Precise Tiling for Uniform Loop Nests

Authors:
Pierre-Yves Calland;Tanguy Risset
Affiliations:
-;-
Venue:
ASAP '95 Proceedings of the IEEE International Conference on Application Specific Array Processors
Year:
1995

Citing 0
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Abstract

The subject of this article is a hyperplane partitioning problem applied to perfect loop nests. This work is aimed at increasing the compu- tation granularity to reduce the overhead due to communication time. This study is different from previous works as it takes redundant communications into account. We propose an algorithm giving the optimal solution and var- ious examples to show the soundness of this report.