Handbook for Digital Signal Processing
Handbook for Digital Signal Processing
A VLSI architecture for image registration in real time
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper a dedicated multiprocessor architecture for a real time implementation of the normalized cross correlation function (NCCF) on images up to 1024x1024 pixels is presented. The computational requirements are dramatically reduced by calculating this algorithm in the frequency domain. In contrast to a standard implementation of the NCCF which inherently imposes rectangular templates, the proposed enhanced method also allows to search for free-form templates which even may include holes. The computation in the frequency domain is based on a single program multiple data (SPMD) architecture which includes a dedicated ASIC for the computation of the 1D complex FFT. Besides this specific part of the system, the image pre- and post- processing tasks are supported by general purpose DSP's. A system consisting of 4 ASIC's and 2 Sharc DSP's is able to compute the enhanced NCCF of a free form template on images of 1024x1024 pixels within 134 ms (8 frames/s).