Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters
Journal of VLSI Signal Processing Systems
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In this paper, a block-update parallel processing algorithm is proposed for increasing the throughput of the CORDIC-based QRD-RLS filtering with low power consumption. The proposed algorithm employs single-state-update parallel processing, and with this algorithm, the throughput of a block-by-block weight-update QRD-RLS filter can be increased at the cost of linear increase in hardware resource, which is the same as in {Ma00}. However, the proposed algorithm does not change the iteration bounds and clock frequency of the QRD-RLS filters {Parhi99}. As a result, the functional units need not be pipelined and the power consumption only increases linearly instead of quadratically as compared to the approach in {Ma00} for throughput increase. Due to non-pipelining and less power consumption, a higher folding factor can be used for a folding transformation {Gao001}, {Gao002} and a great reduction in hardware resource can be achieved without exceeding the physical limitation on pipelining level and power density. Therefore, the proposed algorithm can serve as an important stage in designing and mapping a QRD-RLS filter onto physical hardware or computing resources, and thus is better for both ASIC chip design and parallel computing when block-by-block weight-update is applicable.