Specification and analysis of self-timed circuits
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
OR Causality: Modelling and Hardware Implementation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
Synthesis of speed-independent circuits from STG-unfolding segment
DAC '97 Proceedings of the 34th annual Design Automation Conference
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Signal Transition Graphs(STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on Occurrence nets(OCN) and its prefix, called unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seem as a parallel algorithm for deriving a logic function.