Improving I/O performance with a conditional store buffer
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
A new ultra-low latency message transfer mechanism
CSN '07 Proceedings of the Sixth IASTED International Conference on Communication Systems and Networks
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Fast and efficient communication is one of the major design goals not only for parallel systems but also for clusters of workstations. The proposed model of the high performance communication device ATOLL 1 features very low latency for the start of communication operations and reduces the software overhead for communication specific functions. To close the gap between off-the-shelf microprocessors and the communication system a highly sophisticated processor interface implements atomic start of communication, MMU support, and a flexible event scheduling scheme. The interconnectivity of ATOLL provided by four independent network ports combined with cut-through routing allows the configuration of a large variety of network topologies. A software transparent error correction mechanism significantly reduces the required protocol overhead. The presented simulation results promise high performance and low-latency communication.