Low-power fixed-width array multipliers
Proceedings of the 2004 international symposium on Low power electronics and design
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
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We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed design shows equivalent performance as tree multipliers for n 驴 32. An efficient radix-4 recoding logic generates the partial products in a left-to-right order. The partial products are split intoupper and lower groups. Each group is reduced using [3:2] adders with optimized signal flows and the carry-save results from two groups are combined using a [4:2] adder. The final product is obtained with a prefix adder optimized to match the non-uniform arrival profile of the inputs. Layout experiments indicate that upper/lower split multipliers have slightly less area andpower than optimized tree multipliers while keeping the same delay for n 驴 32.