A unified model for co-simulation and co-synthesis of mixed hardware/software systems

Authors:
C. A. Valderrama;A. Changuel;P. V. Raghavan;M. Abid;T. Ben Ismail;A. A. Jerraya
Affiliations:
TIMA / INPG, System-Level Synthesis Group, 46 avenue Félix Viallet 38031 Grenoble CEDEX, FRANCE;TIMA / INPG, System-Level Synthesis Group, 46 avenue Félix Viallet 38031 Grenoble CEDEX, FRANCE;TIMA / INPG, System-Level Synthesis Group, 46 avenue Félix Viallet 38031 Grenoble CEDEX, FRANCE;TIMA / INPG, System-Level Synthesis Group, 46 avenue Félix Viallet 38031 Grenoble CEDEX, FRANCE;TIMA / INPG, System-Level Synthesis Group, 46 avenue Félix Viallet 38031 Grenoble CEDEX, FRANCE;TIMA / INPG, System-Level Synthesis Group, 46 avenue Félix Viallet 38031 Grenoble CEDEX, FRANCE
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

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Abstract

This paper presents a methodology for a unified co-simulation and co-synthesis of hardware-software systems. This approach addresses the modeling of communication between the hardware and software modules at different abstraction levels and for different design tools. The main contribution is the use of a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes. A system is viewed as a set of communicating hardware (VHDL) and software (C) sub-systems. The same C, VHDL descriptions can be used for both co-simulation and hardware-software co-synthesis. This approach is illustrated by an example.