Integer and combinatorial optimization
Integer and combinatorial optimization
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
MIPS RISC architectures
Synthesis of pipelined instruction set processors
DAC '93 Proceedings of the 30th international Design Automation Conference
MIST—a design aid for programmable pipelined processors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
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In this paper a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that minimizes overall processor cost. In the proposed cost model, processor cost has two components, the cost of hardware necessary to realize the processor and the cost of degraded performance due to pipeline hazards as compared to an ideal pipelined processor. A previous paper detailed the optimization algorithm. This paper extends these results to handle enclosed pairs of instructions having structural hazards. The extended algorithm can produce an optimal result. This algorithm and several examples are presented.